Phase-locked loops (PLLs) have been widely used in high-speed communication systems because PLLs efficiently perform clock recovery or clock generation at a relatively low cost. Dynamic voltage and frequency scaling is a critical capability in reducing power consumption of power sensitive devices. Scaling, in this sense, means the ability to select high performance with nominal power supply voltages and high frequency clock operation or low performance by reducing the power supply voltage and corresponding the clock frequency. Reducing the system power is usually done when performance is not needed or when running from a limited energy source such as a battery. To allow low power operation, the PLL and other circuits must support very aggressive power/energy management techniques. For the PLL, this means low power operation while supporting key required features such as dynamic frequency scaling, dynamic voltage scaling, clock freezing and alternate low frequency clocking. Dynamic implies that the PLL is able to support changes in the output frequency and logic supply voltage without requiring the system to stop operation or waiting for the PLL clock to reacquire lock.
Using a PLL or delay-locked loop (DLL) has advantages in a battery powered system because a PLL is able to receive a lower frequency reference frequency from a stable oscillator to generate system clock frequencies. A PLL also allows changing the system clock frequency without changing the reference frequency.
In switching between two or more clocks in a PLL or other logic system, it is important that the switching be glitch-free. Transients that occur on a clock in a computer system that is not one of the useable edges may be mistaken by the logic system as a valid clock edge and thus create timing problems or system failures. If the two or more clocks are synchronous, which means they are derived from the same reference source, providing glitch-free switching is simpler to achieve. However, if the two or more clocks are not synchronous, glitch-free switching is more difficult. In many logic systems, and in particular PLL clock systems used in a system that employs frequency scaling, there are times when it may be advantageous to switch between asynchronous clocks for the system clock while providing glitch-free switching.
Multi-frequency clocks have been used to enable fractional frequency division. Typically, as shown in the prior art, a frequency synthesizer generates a number of evenly phased clocks that are selected in a multiplexer (MUX) controlled by state machine. The output clock of the MUX extends the last cycle of the count fractionally. The clock then goes through the integer frequency divider resulting in a fractionally divided clock. The prior art state machine is complex requiring two counters, a decoder, and another phase clock MUX. The prior art mentions that the transitions from phase 01 to phase 02 occurs after sensing that phase 01 goes from a logic one to a logic zero and after phase 02 to those from a logic one to a logic zero. However, there is no mechanism shown to perform the required phase switching. The prior art does not address the difficulties of transitioning from phases 01 to phase 04, sensing the transition of phase 01 from a logic one to a logic zero and then sensing the transition of phase 04 from a logic zero to a logic one and then from a logic one to a logic zero.
There is, therefore, a need for a circuit that allows fractional frequency division of a clock by selectively switching glitch free between phases of clock defining the resolution of fractional division.